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Technical Reference Notes AIF12W300 DC-DC Series
AIF12W300, 600W, DC-DC Converter Module
The single output AIF is an isolated, single output DC to DC converter module, providing up to 600W output with a maximum baseplate operating temperature of 100C with no derating. The AIF features full safety isolated low voltage secondary side control and Astec Linear Programming (ALPTM) or through I2C bus for convenient adjustment of the module's parameters.
Electrical Parameters
Input Input range Input Surge Efficiency Output Regulation Noise / Ripple Control Voltage Adjust Enable Current Limit Adjust Over Voltage Protection Adjust 250 - 420 VDC 500V / 100ms 91.8% (Typical)
0.2% typical down to no load 480mV typical 80 to 120% TTL compatible (positive & negative enable options) 20% to 100% 110% to 150% VO
Special Features
* * * * * * * * * 600W continuous power at 100C baseplate temperature 108W/in3 (6.6W/cm3) High efficiency - 91.8% typical Low output ripple and noise Positive and Negative Enable function Excellent transient response OVP, OCP, V Adj control with ALPTM analog mode linear control, or through I2C bus for digital mode control. Paralleable with accurate current sharing Switching Frequency 400KHz
Safety
UL, cUL TUV 60950 Recognized EN60950 Licensed
Environmental Specifications
-20C to 100C Operating Baseplate Temperature -55C to 125C Storage Temperature MTBF > 0.3Mhours Pb-free reflow compatible and ROHS Compliant
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Technical Reference Notes AIF12W300 DC-DC Series
Electrical Specifications
STANDARD TEST CONDITION on a single unit, unless otherwise indicated, electrical specifications apply over all operating input voltage and temperature conditions. Tamb Vin Enable CLK IN CLK OUT CSHARE Iout AUX OUTPUT -Sense V ADJ C MON TEMP MON C LIM ADJ OVP ADJ PG/ID I/P Cap requirement ABSOLUTE MAXIMUM RATINGS Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the IPS. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Input Voltage: Continuous: Transient (100ms) Operating Baseplate Temperature Start up Baseplate Temperature Storage Temperature Operating Humidity I/O Isolation Symbol VI VI, trans Tc TSTG Min 250 -20 -40 -55 15 2700 Typ Max 420 500 100 100 125 95 Unit Vdc Vdc C C C % Vdc 25C 300 V 2% Open Open Open Open 75% Io max 2% Open connect to -Vout Open Open Open Open Open Open 68F/450V min.
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Technical Reference Notes AIF12W300 DC-DC Series
INPUT SPECIFICATIONS Parameter Operating Input Voltage Undervoltage Threshold (IO = 10% IO max)
Turn-on point Turn-off point
Symbol VI
Min 250
Typ 300
Max 420
Unit Vdc
Input Current 1 (VI = VI min, IO = IO max, VO = VO nom) (VI = 0 to VI max, IO = IO max, VO = VO nom) Input Reflected Ripple Current 2 (5Hz to 20MHz: 12H source impedance: Tamb = 25C) Inrush Transient 3 Break Regulation CLK IN Frequency Voltage Level (internal ac coupled) Enable Positive Logic Low Logic - Module Off High Logic - Module On (Enable pin opened) Enable Low Sourced Current (Venable = 0.7V) Turn-On Delay No load input power Turn-On Time (IO = IO max ; VO within 1%) (No external O/P capacitance) Input Capacitance
II max II max II I2t -
205 175 -
30
245 215 2.8 3.4 -
V V A A mApk-pk A2s V kHz Vpk-pk
720 3.3
215 800 -
2.8 245 880 5.5
Venable Venable -
0 2 -
0.6
0.7 10 150 380 5 650 0.8
V V A mS W mS F
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Technical Reference Notes AIF12W300 DC-DC Series
OUTPUT SPECIFICATIONS Parameter Output Voltage Setpoint (VI min to VI max: IO = IO max ; Tamb = 25C ) Output Regulation: Line Load Output Voltage Adjust 4, 5 Vadj = 0V Vadj = 2V Output Ripple and Noise Peak-to-Peak (5 Hz to 20MHz) External Load Capacitance Switching Frequency Output Power Efficiency (VI = VI nom, IO = IO max, Tamb = 25C) Output Current Output Current-limit Inception (Hiccup) (VO = 97% VO set nom) Output Current Limit Adjust 5 Output Current Monitor Imon at IO max Monitored IO Range Imon Compliance Voltage Current Share Accuracy 6 (Cshare connected together, IO 80%IO max) No. of Parallel Unit Over Current Protection Level (VO dropped to 97% of VO nom) Over Voltage Protection Level Over Voltage Protection Adjust 5 Over Temperature Protection Trip Point (Baseplate temperature) Internal Temperature Monitor Temperature Coefficient Source Impedance Temperature Coefficient (TC = -40C to 100C) Symbol VO set Min 47.52 Typ 48 Max 48.48 Unit V
PO IO IO -
78 118 360 90 0 105 20 0.9 20 105 120 120 105 9.8 -
80 120 110 400 91.8 1.0 3 110 125 10.0 1.0 -
0.2 0.2 82 122 480 2000 440 600 12.5 120 100 1.1 100 5.0 5 10 115 130 150 120 10.2 0.02
% % %VO %VO mVpk-pk F kHz W % A %IO %IO
max max
mA %IO max V %I avg pcs %IO max %VO %VO C mV/C k %VO/C
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Technical Reference Notes AIF12W300 DC-DC Series
OUTPUT SPECIFICATIONS (continued) Parameter Step-load Excursion (25% to 75% load change @ 1A/S, recovery to 1%VO; VI = VI nom; Tamb = 25C) Output Overshoot Output Undershoot Step Load Response (25% to 75% load change @ 1A/S, recovery to 1%VO; VI = VI nom; Tamb = 25C; measure from end of transition) Turn-on Output Voltage Overshoot (IO = IO max ; Tamb = 25C; no external O/P capacitor) Short Circuit Current (Hiccup Mode) CLK OUT Frequency Voltage Level (internal ac coupled) No. of Fan Out Unit Turn-Off Negative Voltage (resistive loading, wire length of 10cm) AUX Output Voltage AUX Output Current 7 AUX Output Voltage Ripple and Noise Power Good Monitor / Identification PG/ID Low (Power Fault, Isink 10mA) PG/ID Internal Pull-up Resistance to VO Symbol Min Typ Max Unit
-
-
-
2.4 2.4 250
V V S
-
720 3.3 10.5 46
3 800 12 47
5 150 880 5.5 2 -0.7 13.5 10 600 0.2 48
%VO %IO
max
kHz Vpk-pk pcs V V mA mV V k
Notes: 1. An input line fuse is recommended for use (e.g. Littelfuse type, 10A 250V FB). 2. External input capacitance required. See Figure 1 for the Input Reflected-Ripple Current Test Setup. Measure input reflected-ripple current with a simulated source inductance of 12H. 3. See Figure 2 for the Inrush Current Test Setup. Measure input inrush current with a simulated source inductance of 12H and input bulk capacitor of 68F/450Vmin must always be added. 4. The combination of remote sense and trim do not exceed a total of 0.5V. 5. Refer to Basic Operation and Features section. 6. See Figure 3 for modules in parallel connection. 7. The AUX output pin does not allow for any short circuit and OCP testing.
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Technical Reference Notes AIF12W300 DC-DC Series
Electrical Specifications (continued)
ISOLATION SPECIFICATIONS
Parameter Isolation Capacitance Device Symbol Min Typ Max Unit
Isolation Resistance SAFETY AGENCY
Parameter
All All
-
10
300 -
-
PF M
Device
Safety Approval
All
UL/cUL 60950, 3rd Edition - Recognized EN 60950 through TUV
SHOCK AND VIBRATION Vibration test Endurance random vibration (non-operating) Random vibration shall be applied at the following test condition: Frequency range PSD Acceleration Duration 10 - 200Hz; 200 - 2000Hz 0.01g2/Hz; 0.003g2/Hz 2.5g RMS (typical level) 20 mins per axis
Endurance random vibration (operating) Random vibration shall be applied at the following test condition with the unit at operating mode at nominal lines and full load condition, with POK monitored: Frequency range PSD Acceleration Duration Shock test The non-operating test condition is selected as typical of: Acceleration Pulse Duration Directions 30g Halfsine 6ms minimum all 6 faces, 3 times in each positive and negative directions 10 - 500Hz 0.002g2/Hz flat 1g RMS 20 mins per axis
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Technical Reference Notes AIF12W300 DC-DC Series
Electrical Specifications (continued)
Shock test The operating test condition is selected as typical of: Acceleration Pulse Duration Directions 4g Halfsine 22ms minimum all 6 faces, 3 times in each positive and negative directions
ESD Contact discharge Air discharge 6KV 8KV
EMC (CONDUCTED) FCC Class A and CISPR22 Class A - This is a system test and not a component level test. See Figure 4 for EMI Filter Schematic.
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Technical Reference Notes AIF12W300 DC-DC Series
Electrical Specifications (continued)
Figure 1. Input Reflected-Ripple Test Setup
Figure 2. Inrush Current Test Setup
Figure 1. Input Reflected-Ripple Current Test Setup
Figure 2. Inrush Current Test Setup
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Electrical Specifications (continued)
Single Module Operation
Parallel Module Operation Figure 3. Module Connections for Single and Parallel Operation
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Technical Reference Notes AIF12W300 DC-DC Series
Electrical Specifications (continued)
Figure 4. EMI Filter Schematic for AIF Series
Figure 5. EMI Filter Scan (without Filter)
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Technical Reference Notes AIF12W300 DC-DC Series
Performance Curves
AIF12W300
Efficiency vs. Output Current 95% 90% 85% Efficiency [%] 80% 75% 70% 65% 60% 55% 0 2 4 6 8 Output Current [A] 10 12
Vin = 250Vdc Vin = 300Vdc Vin = 420Vdc
Pow er Dissipation vs. Output Current 70 60 Power Dissipation [W] 50 40 30 20 10 0 0 2 4 6 8 Output Current [A] 10 12
Vin = 250Vdc Vin = 300Vdc Vin = 420Vdc
Figure 6. Efficiency vs. Load Current at Ambient Temperature (TA) = 25C.
Figure 7. Power Dissipation vs. Load Current at Ambient Temperature (TA) = 25C.
Figure 8. Output Ripple Waveform, Vin = 300V, Io = 12.5A, at Ambient Temperature (TA) = 25C.
Figure 9. Clock Out Waveform, Vin = 300V, Io = 12.5A, at Ambient Temperature (TA) = 25C.
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Performance Curves
AIF12W300 (continued)
Figure 10. Transient Response-Vout Deviation (Hi-Lo) at Ambient Temperature (TA) = 25C.
Figure 11. Transient Response-Vout Deviation (Lo-Hi) at Ambient Temperature (TA) = 25C.
Figure 12. Turn-on Time (Enable to Output) at Ambient Temperature (TA) = 25C.
Figure 13. Turn-on Time (Input to Output) at Ambient Temperature (TA) = 25C.
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Technical Reference Notes AIF12W300 DC-DC Series
Basic Operation and Features
Remote Sense (+SENSE, -SENSE) Connect the +SENSE and -SENSE pins of the module directly to the load to allow the module to compensate for the voltage drop across the conductors carrying the load current. If remote sensing is not required (for example if the load is close to the module) the sense pins should be connected directly to the module's output pins to ensure accurate regulation. Note: If the sense leads fail open circuit, the module will revert to local sense at the output pins. Incorrect connection of sense leads may damage the module. Remote Sense compensation at nominal VO only.
Enable Control (ENABLE) The enable pin is a TTL compatible input used to turn the output of the module on or off. The output is enabled when the ENABLE pin open or driven to a logic high >2V, and disabled when the ENABLE pin is connected to -SENSE or driven to a logic low of < 0.7V.
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Basic Operation and Features (continued)
Output Voltage Adjustment (V ADJ) The output voltage of the module may be accurately adjusted by up -20%, +20% of the nominal factory set output. Adjustment is carried out using either an external voltage source (0 to 2V, capable of sinking 1mA) or resistor (0 to 2K) connected between VADJ and -SENSE.
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Basic Operation and Features (continued)
Current Limit Adjustment (C LIM ADJ) A constant current limiting circuit protects the module under overload or short circuit conditions. With the C LIM ADJ pin left unconnected, the current limit is factory set to 115% of the module's rated output. Current limit may be adjusted across the range from 20% to 100% using an external voltage source (0.8 to 4V, capable of sinking 1mA) or a resistor (800R to 4K) connected between C LIM ADJ and -SENSE.
Overvoltage Protection Adjustment (OVP ADJ) An independent overvoltage circuit monitors the module's output pins and will shut the module down in the event of an internal or external fault which causes the output voltage to rise above the preset limit. The module is reset by removing and re-applying the input power or toggle the ENABLE OFF/ON. The overvoltage set point may be adjusted between 20% and 50% above the output voltage (VO), and automatically track adjustments made to the output voltage using V ADJ. OVP ADJ should be used to increase the OVP margin when the voltage drop between power output pins and remote sense is more than 0.2V.
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Technical Reference Notes AIF12W300 DC-DC Series
Basic Operation and Features (continued)
Power Good / Identification (PG/ID) This pin provides an indication that the module's converters are working, and can also be used to identify the factory set output voltage of the module. The PG/ID pin goes high to the level of the output voltage (VO) to indicate that the module is operating and delivering power. The output goes low if the converters stop operating due to a fault such as an overtemperature or overvoltage condition. The PG/ID pin will also go low if the module is disabled via the ENABLE pin or under light load condition.
The resistance between the PG/ID pin and the +ve output of the module can be used to identify the module with no power applied according to the table: Model Number AIF12W300-L AIF12W300N-L AIF12W300-NTL AIF12W300N-NTL Resistance (k) 47 47 47 47
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Basic Operation and Features (continued)
Clock Signals (CLK IN, CLK OUT) The module's internal clock is accurate and stable over its full operating range and synchronization is not normally required, but it can reduce noise in paralleled systems. Clock signals can be wired in series (the CLK OUT pin of one module to the CLK IN pin of the next etc) in which case all the modules will be synchronized with the first module in the chain. Alternatively, an external clock signal of 5Vpk-pk at 800KHz 10% can be connected to the CLK IN pins of all the modules. If the clock input to any module fails, the module will automatically switch back to its internal clock and will continue to operate normally. The CLK IN and CLK OUT signals are AC coupled, so any module can clock another module regardless of polarity.
Current Share (CSHARE) To ensure that all modules in a parallel system accurately share current, the C SHARE pins on each module should be connected together. The voltage on the C SHARE pins represents the average load current per module. Each module compares this average with its own current and adjusts its output voltage to correct the error. In this way the module maintains accurate current sharing. Note: The -SENSE and +SENSE pins of each module must also be connected together to ensure accurate current sharing.
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Basic Operation and Features (continued)
Current Monitoring (C MON) The C MON pin provides an indication of the amount of current supplied by the module. The output of the C MON pin is a current source proportional to the output current of the module, where 0.2 to 1mA = 20 to 100% Iorated. The C MON output can be paralleled with C MON outputs from other modules to indicate the total current supplied in a paralleled system.
Temperature Monitoring (TEMP MON) The TEMP MON pin provides an indication of the module's internal temperature. The voltage at the TEMP MON pin is proportional to the temperature of the module baseplate at 10mV per C, where: Module temperature (C) = (Vtemp mon X 100) - 273 The temperature monitor signal can be used by thermal management systems (e.g. to control a variable speed fan). It can also be used for overtemperature warning circuits and for thermal design verification of prototype power supplies and heatsink.
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Technical Reference Notes AIF12W300 DC-DC Series
Basic Operation and Features (continued)
Break Regulation AIF12W300-Series modules are designed to deliver full rate output current at up to 0.5V above VO nom at the minimum specified input voltage.
I2C Digital Control (DCS, I2C CLK, I2C DATA) The module shall be capable to be controlled by I2C interface, which is SMBus compatible, via I2C CLK and I2C DATA pins. These two pins share the same pin location of CLIM ADJ and V ADJ pins respectively. Digital control is selected when Digital Control Select (DCS) pin voltage is between 2V to 4V. When digital control is selected, analog adjust pin function is disabled. DCS signal shall only be applied when the module is powered off or disabled. An external 10k pull-up resistor is necessary for each I2C CLK, and I2C DATA pin, for 100kHz I2C bus frequency.
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Basic Operation and Features (continued)
I2C COMMUNICATION PROTOCOL 1. Command word Command word is sent by master system to inform slave device that what kind of operation the master like to do. It is a 16-bit data. Bit 0 to bit 9 indicate the data need to transfer (e.g. the value of OV_ADJ). As there are two different lengths of data, one is 8-bit and the other is 10-bit. So, if 10-bit data is transmitting/receiving, whole 10 bits (DATA9 - DATA0) will be used. In 8 bits case, only the least significant 8 bits (DATA7 - DATA0) will be used. The two bits (DATA9 and DATA8) will be cleared. The 5 bits (REG4 - REG0) indicate which command needs to. When the master requests data from the slave, the DATA9DATA0 bits should be cleared. And during setting the four information items (Model Name, Serial No., Firmware Version, Model Revision), DATA9-DATA8 should be cleared and is followed by the actual data. The format of the 16-bits command word is as follow:
Bit 15 DSR Bit 7 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 REG4 REG3 REG2 REG1 REG0 DATA9 Bit 8 DATA8 Bit 0 DATA0
The DSR (Data Set Read) bit controls read/write of data. If the master send a 0 (write operation) for this bit, the slave device will get the command register and data. And then set the value of the corresponding command register. If the master sends a 1 (read operation) for this bit, the slave device will get the current value of the corresponding command register and send it to the master. The table below shows the register mapping: Command Register MODEL_NO (read/write*) SERIAL_NO (read/write*) FIRMWARE_VER (read/write*) MODEL_REV (read/write*) SLAVE_ADDRESS (read/write) OVP_ADJ (read/write) V_ADJ (read/write) CLIM_ADJ (read/write) TMON (read only) VOUT (read only) CMON (read only) RESET (write only) LOCK (write only*) UNLOCK (write only*) Coding (REG4 - REG0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01111 10000 10001
* Remark: write functions only used to production.
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I2C COMMUNICATION PROTOCOL (continued) 2. Data Transfer Structure on I2C Bus Terms Stt Sadd Ack Bt-H Bt-L StD(1st, 2nd,...nth) Stp Description Start bit Slave address Acknowledge Higher byte Lower byte String of bytes(1st byte, 2nd byte,......nth byte) Stop Bit No. of bits 1 8 1 8 8 8 1
In the block diagram below, gray boxes indicate master-send signal; white boxes indicate slave-send signal.
Master Slave
2.1 Set data to slave
SCL
SDA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Salve Address Start bit
Command byte (high)
Command byte (low)
Stop bit
Wait for ack. signal
Fig 1.1 SCL and SDA signal in write mode.
S
SAdd
Ack
Bt-H (command)
Ack
Bt-L (command)
Ack
Stp
Fig 1.2 Block diagram of write mode.
Procedures: 1. The master device gives a Start condition via SDA. 2. Master sends the 8-bit slave address in which bit 0 of it should be 0 (0 indicate a write condition to slave) via SDA. 3. The addressed slave device give out acknowledge via SDA. 4. The master sends the high byte of command code via SDA. 5. The slave give out acknowledge via SDA. 6. The master sends the low byte of command code via SDA. 7. Slave gives out acknowledge after receiving the last byte. 8. Master gives a STOP condition via SDA to stop the transaction.
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Technical Reference Notes AIF12W300 DC-DC Series
SCL
SDA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Salve Address Start bit
Command byte (high)
Command byte (low)
Stop bit
Wait for ack. signal SCL
SDA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Salve Address Start bit
Data byte receive (high)
Data byte receive (low)
Stop bit
Give back ack. signal
Give back NO ack. signal
Fig. 2.1 SCL and SDA signal of read mode (2 bytes of data read).
S S
SAdd SAdd
Ack Ack
Bt-H (command) Bt-H (data) Ack
Ack
Bt-L (command) Bt-L (data) Ack
Ack Stp
Stp
Fig. 2.2 Block diagram of read mode (2 bytes of data read).
2.2 Read data from slave (2-byte data) Procedures: 1. The master device gives out a start condition on SDA. 2. Master sends the 8 bits slave address which bit 0 of it should be 0 (0 indicates write mode for slave) via SDA. 3. The addressed slave device gives back acknowledge via SDA. 4. Master sends out the high byte of the 2-bytes command word. 5. Slave device gives back acknowledge again. 6. Master sends out the low byte of the 2-bytes command word. 7. Slave device gives back acknowledge again. 8. Master sends out a stop condition to prepare for the next transaction. 9. Master gives out a start condition again for the next transaction. 10. Master sends the 8 bits slave address which bit 0 of it should be 1(1 indicates read mode for slave) via SDA. 11. Slave give back an acknowledge. 12. Slave then sends out the high byte of desired data. 13. Master gives back acknowledge to slave.
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Technical Reference Notes AIF12W300 DC-DC Series
14. Slave sends the low byte of the desired data.
SCL
SDA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Salve Address Start bit
Command byte (high)
Command byte (low)
Stop bit
Give back ack. signal SCL
......
SDA A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
......
D7 D6 D5 D4 D3 D2 D1 D0
Salve Address Start bit
String Data (1st) receive
String Data (last byte) receive
Stop bit
Give back ack. signal
Give back NO ack. signal
Fig 3.1 SCL and SDA signal of read mode (String of data).
S S SAdd SAdd Ack Ack Bt-H (command) StD(1st) Ack Ack StD(2nd) Bt-L (command) Ack Ack Stp Ack Stp
......
StD(nth)
Fig 3.1 Block diagram of read mode (String of data).
15. Master gives back acknowledge and sends out a stop condition to close the transaction. 2.3 Read data from slave (string of data) Procedures: 1. The master device gives out a start condition on SDA. 2. Master sends the 8 bits slave address which bit 0 of it should be 0 (0 indicates write mode for slave) via SDA. 3. The addressed slave device gives back acknowledge via SDA. 4. Master sends out the high byte of the 2-bytes command word. 5. Slave device gives back acknowledge again. 6. Master sends out the low byte of the 2-bytes command word. 7. Slave device gives back acknowledge again. 8. Master sends out a stop condition to prepare for the next transaction. 9. Master gives out a start condition again for the next transaction. 10. Master sends the 8 bits slave address which bit 0 of it should be 1(1 indicates read mode for slave) via SDA. 11. Slave give back an acknowledge. 12. Slave then sends out the first byte of desired data.
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13. Master gives back acknowledge to slave. 14. Repeat 12 and 13 until the end of bytes. 15. Master gives back acknowledge and sends out a stop condition to close the transaction.
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Basic Operation and Features (continued)
DIGITAL CONTROL DEMO USER GUIDE This Demo program is developed to test and evaluate I2C control features of AIF-300 DC/DC modules. Equipment required: 1. One or more modules of AIF-300 series. 2. PC - Module interface hardware. 3. PC (with windows 98 / Me inside) Hardware setup: The picture shown below is the setup of the hardware.
PC - I2C
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DIGITAL CONTROL DEMO USER GUIDE (continued) Software Setup: 1. Click on the program "Ampss68.exe". Then following dialog box shows:
2. Click on "Setup" and choose "Parallel Port Address".
Then a new dialog box shows and enter the right value into it and click "OK":
Enter the value in HEX here
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3. Then click on "Setup" and choose "Pulse Constant".
Also set the desired pulse constant value into the dialog box below and click "OK":
Enter the value in DEC here 4. Select Module: Enter the slave address of the module that you want to control:
Enter the corresponding slave address here.
Note: "0" and "1" are the globe address of MMIIC. So, it can only perform "write" function when the UUT address is set
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to 0 or 1. 5. Write Value:
These four items only used to production. If needed to change items clicked "Unlock" at first, and then choose one item to change its value.
Choose one of these four items to change its value. Click here when finished choosing the one of the above items. Choose "Reset" to restore all the default setting except the slave address
"Lock" and " Unlock" only used to production. When needed to change items "Model", "Serial", "Firmware", "Model rev" value, chose "Unlock". When items change is completed, clicked "Lock".
Click on the circle beside the desired item that needs to be changed its value. After choosing the desired item, click on "Write" below the items. Then a new dialog box shows (except "Reset" option).
Enter the desired value
Fill the box with the new value and click "OK". Or click "Cancel " to cancel this operation.
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6. Read Value: Double click on the item box to read the corresponding value:
Double click the item box to read its value.
7. Exit Program: Click on "Setup" and choose "Exit" to exit the program.
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Basic Operation and Features (continued)
PC-I2C INTERFACE CIRCUIT DIAGRAM
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Basic Operation and Features (continued)
5V VCC2 10u 1k 5V VCC1 10u 1k 1k 1k 1k 6N137 2 2N7002 3 5 7 7 I2C SDA 2N7002 100n 2N7002 I2C RTN 8 6N137 1k 1k 5 3 6 2 2N7002 1k 6 -SENSE (AIF) 8 100n 2N7002 2N7002 I2C DATA (AIF) 1k
1k
1k
1k
1k 6N137 2 8
2N7002 100n 2N7002 6 3 5 7 7 1k
I2C CLK (AIF)
2N7002
I2C SCL 2N7002 100n 2N7002
5 3 6 2 6N137 2N7002
8
RECOMMENDED OPTO ISOLATION CIRCUIT
PARALLEL OPERATION WITH OPTO ISOLATION
MODEL: AIF12W300 SERIES JUNE 2006 SHEET 31 OF 37
Technical Reference Notes AIF12W300 DC-DC Series
Basic Operation and Features (continued)
DIGITAL CONTROL The module shall be capable to be controlled by I2C interface, which is SMBus compatible, via I2C CLK and I2C DATA pins. These two pins share the same pin location of CLIM ADJ and V ADJ pins respectively. Digital control is selected when Digital Control Select (DCS) pin voltage is between 2V - 4V. There are 7 command registers for read operation, 4 command registers for read/write operation and 1 command register for write operation. Command Register MODEL_NO (read only) SERIAL_NO (read only) FIRMWARE_VER (read only) MODEL_REV (read only) SLAVE_ADDRESS (read/write) OVP_ADJ (read/write) V_ADJ (read/write) CLIM_ADJ (read/write) TMON (read only) VOUT (read only) CMON (read only) RESET (write only) DIGITAL DATA CONVERSION Each control and monitoring data is in 10-bit format. The data conversion formulae are as follows. OVP_ADJ: The range of the OVP_ADJ can be adjusted from 125% to 145% of VO (nom). The received/transmitted data is calculated by the equation below. Receive Data (from module to PC): Input Data: MCU OVPadj (integer) Output Data: OVPadj% (round to 1decimal place)
OVPadj% = 145% - MCU OVPadj x 20% 205
Description Read model name of the module Read serial number on bar code label Read firmware version Read model revision Read or set slave address of the module Read or set overvoltage protection threshold of the module Read or set output voltage of the module Read or set current limit protection threshold of the module Read baseplate temperature of the module Read output voltage of the module Read output current of the module Reset all control parameters to factory setting
Transmit Data (from PC to module): Input Data: OVPadj (round to 1 decimal place) Output Data: MCU OVPadj (integer)
MODEL: AIF12W300 SERIES JUNE 2006
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Technical Reference Notes AIF12W300 DC-DC Series
MCU OVPadj = 145% - OVPadj% x 205 20%
DIGITAL DATA CONVERSION (continued) V_ADJ: 1. V_adj range between 80% to 120% module: (5Vo and above model) The range of the V_ADJ can be adjusted from 80% to 120% of VO (nom). The received/transmitted data is calculated by the equation below. Receive Data (from module to PC): Input Data: MCU Vadj (integer) Output Data: Vadj% (round to 1decimal place)
Vadj% = 80% +
MCU Vadj x 40% 410
Transmit Data (from PC to module): Input Data: Vadj (round to 1 decimal place) Output Data: MCU Vadj (integer)
MCU Vadj = Vadj% - 80% x 410 40%
2. V_adj range between 50% to 110% module: (Below 5Vo model) The range of the V_ADJ can be adjusted from 50% to 110% of VO (nom). The received/transmitted data is calculated by the equation below. Vadj between 50% ~100% Receive Data (from module to PC): Input Data: MCU Vadj (integer) Output Data: Vadj% (round to 1decimal place)
Vadj% = 50% +
Transmit Data (from PC to module): Input Data: Vadj (round to 1 decimal place) Output Data: MCU Vadj (integer)
MCU Vadj x 50% 205
MCU Vadj =
Vadj% - 50% x 205 50%
MODEL: AIF12W300 SERIES JUNE 2006
SHEET 33 OF 37
Technical Reference Notes AIF12W300 DC-DC Series
DIGITAL DATA CONVERSION (continued) Vadj between 100% ~110%. Receive Data (from module to PC): Input Data: MCU Vadj (integer) Output Data: Vadj% (round to 1decimal place)
Vadj% = 100% +
Transmit Data (from PC to module): Input Data: Vadj (round to 1 decimal place) Output Data: MCU Vadj (integer)
MCU Vadj - 205 x 10% 205
MCU Vadj =
CLIM_ADJ:
Vadj% - 90% x 205 10%
The range of the CLIM_ADJ can be adjusted from 0% to 102.5% or 110% of rated IO. The received/transmitted data is calculated by the equation below. Receive Data (from module to PC): Input Data: MCU CLIMadj (integer) Output Data: CLIMadj% (round to 1decimal place) Case 1: MCU CLIMadj 841
CLIMadj% = MCU CLIMadj x 102.5% 840
Case 2: MCU CLIMadj >= 841
CLIMadj% = 110%
Transmit Data (from PC to module): Input Data: CLIMadj (round to 1 decimal place) Output Data: MCU CLIMadj (integer) Case1: CLIMadj% 110% Case2: CLIMadj% >= 110%
MCU CLIMadj = CLIMadj% x 840 102.5%
MCU CLIMadj = 841
MODEL: AIF12W300 SERIES JUNE 2006
SHEET 34 OF 37
Technical Reference Notes AIF12W300 DC-DC Series
DIGITAL DATA CONVERSION (continued) TMON: Baseplate temperature monitoring is a read only data. It is ranged from -40C to 120C. The temperature of module can be calculated by the equation below: Receive Data (from module to PC): Input Data: MCU Tmon (integer) Output Data: Baseplate Temperature in C (round to 1 decimal place) MCU Tmon Baseplate Temperature in C = x 500 - 273 1024
VOUT: Output Voltage is a read only data. The output voltage can be calculated by the equation below: Receive Data (from module to PC): Input Data: MCU Vout (integer) Output Data: Output Voltage in %Vonom (round to 1 decimal place)
Output Voltage in %Vonom = MCU Vout x 100% Vo _ REF
Module name AIF120Y300-L/N-L/-NTL AIF120F300-L/N-L/-NTL AIF80A300-L/N-L/-NTL AIF50B300-L/N-L/-NTL AIF40C300-L/N-L/-NTL AIF25H300-L/N-L/-NTL AIF12W300-L/N-L/-NTL
Vo_REF 369 676 813 820 830 820 820
MODEL: AIF12W300 SERIES JUNE 2006
SHEET 35 OF 37
Technical Reference Notes AIF12W300 DC-DC Series
DIGITAL DATA CONVERSION (continued) CMON: Current monitoring is a read only data. It is ranged from 0% to 100% of rated IO. The output current of module can be calculated by the equation below: Receive Data (from module to PC): Input Data: MCU Cmon (round to 1 decimal place) Output Data: Output Current Monitor in % IO max (integer)
Output Current Monitor in %Iomax = MCU Cmon x 100% 614
DEFAULT FACTORY SETTING Control data Slave address OVP_ADJ V_ADJ CLIM_ADJ Factory Setting 0010100000 (A0h = 160) (8 bit addressing) 0011001101 (00CDh = 205) (125% of VO) 0011001101 (00CDh = 205) (100% of VO (nom) ) 1111111111 (0349h = 841) (110% of rated IO)
MODEL: AIF12W300 SERIES JUNE 2006
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Technical Reference Notes AIF12W300 DC-DC Series
Mechanical Specifications
Parameter Dimension Device All Symbol L W H Min Typ 4.60 [116.8] 2.40 [61.0] 0.50 [12.7] 250 Max Unit in [ mm ] in [ mm ] in [ mm ] g [oz]
Weight
All
Input 31. Positive 32. Negative
PIN ASSIGNMENTS Output Control Pins 21. Positive 1. AUX 22. Positive 2. TEMP MON 23. Positive 3. C MON 24. Positive 4. C SHARE 25. Negative 5. CLK OUT 26. Negative 6. CLK IN 27. Negative 7. PG/ID 28. Negative 8. C LIM ADJ/I2C CLK 9. OVP ADJ/DCS 10. V ADJ/I2C DATA 11. ENABLE 12. - SENSE
PART NUMBERING SCHEME AIF "AIF" = Astec Integrated Full Brick Series O/P CURRENT xxx O/P VOLTAGE x Vin 300 Enable x "N" = Negative Logic Enable No suffix = Positive Logic Enable Suffix NT Suffix
12 = 12.5A
W = 48V
300V DC
"-L" or "L" = "-NT" = Non- Rohs Compliance thread mounting hole
MODEL: AIF12W300 SERIES JUNE 2006
SHEET 37 OF 37
Technical Reference Notes AIF12W300 DC-DC Series
Mechanical Specifications (continued)
Figure 14. Mechanical Outline Drawing
Figure 14. Mechanical Outline Drawing
Please call 1-888-41-ASTEC for further inquiries or visit us at www.astecpower.com
MODEL: AIF12W300 SERIES JUNE 2006 SHEET 38 OF 37

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